09:00

FPGAs reduce system cost and development time significantly

FPGA technology provides a powerful platform with great flexibility and performance. Making use of these advantages allows development of complex high performance embedded products with significant reduction in system cost and development time.

Presenter: Håvard Pedersen Alstad, Data Respons Norge AS

Håvard graduated from the University of Oslo with a M.Sc. in microelectronics in 2008. He works as a Development Engineer at Data Respons, specializing in FPGA development.

09:30

Will FPGA process advantage lead into the Embedded Market?


This presentation will discuss how the new FPGAs with embedded MCUs could change the Embedded Market, particularly when performance, time to market, or customization are key requirements.

So if you are an engineer who either think that an MCU and SW always is the best solution, or if you are an HW designer who think that an ASIC/FPGA solves all your problems, now it is time to rethink.

The new Xilinx Zynq with integrated dualcore ARM Cortex - A15 have at least two generations of process advantage over the traditional MCU ASSP integrators. Not only Xilinx but also Altera will have these FPGA MCU integrations during fall 2011. And in the lower segment more FPGA vendors, like MicroSemi (Actel), have embedded ARM Cortex M series.

The topics that will be discussed in the presentation are:
* Design flexibility - HW/SW design tradeoffs
* HW module integration - SoC/IP Cores support
* Possibility to make field/remote upgrades, for both SW and HW
* Integration with industry standard tools
* Total product cost vs. performance

Presenter: Tryggve Mathiesen, Informasic

Tryggve Mathiesen is CTO of Informasic. He has a high competence and a long experience in the tech industry, not least as an educator/trainer, and there are many persons who have learned from him how to make an efficient product development. Before Informasic he has been at BitSim, XDIN, TietoEnator, Sigma and Saab Space. He holds a M.Sc. degree from Chalmers University.

10:00

Break

10:30

Using Alternative Models of Computation to Simplify FPGA Programming

The FPGA industry continues to grow. Early in the growth cycle it was compared to ASIC technology, primarily because it was used in ASIC prototyping. Presently, FPGAs are also being used in DSP applications as the dedicated resources of the modern FPGA become more DSP-centric. With these hardware innovations well underway, FPGA design tools struggle to catch up with the hardware advances. Exemplified by the need for high-level synthesis and a number of companies trying to tackle the problem, it is clear that common RTL is not the solution to growing complexity and FPGA proliferation. Using new models of computation like dataflow, and multirate asynchronous methodologies, FPGAs have the potential to be utilized direct by algorithm designers instead of the two-step process of algorithm design then RTL reimplementation done by separate engineers. This session will explain some pertinent models of computation and how they can be applied to FPGA implementations. 

Presenter: Johan Olsson, Senior Direct Sales Manager,
National Instruments

11:00

Single chip devices for Low Power SoC Solutions
Based on FPGA's with ARM

The latest technology single chip devices create a full digital system on chip integrating Flash FPGA technology together with an ARM processor. The inherent characteristics give a very low power using low power

SmartFusion mixed signal devices integrates an FPGA, ARM Cortex-M3, and Programmable Analog on a single chip.
As it is based on Flash technology SmartFusion is ideal for hardware and embedded designers who need flexibility and true system on chip solutions and Low Power.
SmartFusion integrates a complete Microcontoller Subsystem including 32-bit ARM Cortex-M3 CPU (100MHz), embedded memories, communication peripherals, etc.
The FPGA array allows you to be flexible and innovative with exactly the features you need.
SmartFusion can be used as a single platform for a variety of product lines, integrating design environment for both FPGA and embedded designers and giving the designer the unique possibility to tradeoff between hardware and software.

Presenter: Rouzbeh Hosseinalikhani, Microsemi Corporation

Rouzbeh is Senior Field Application Engineer at Microsemi covering the Nordic region, with focus on FPGAs and SOC systems. He has over 10 years experience from the semiconductor industry and previous held positions as FPGA and ASIC developer among others at Ericsson.
Rouzbeh Holds a B.Sc.EE degree from KTH.

11:30

13:30

The first Extensible Processing Platform (EPP)

Processor-centric solutions, including microprocessors, ASICs, ASSPs, and applications processors, are a dominant force in today's embedded market. Many of these products are designed as system-on-chip (SoC) solutions, including a core processor engine that is complemented by common- and application-specific IP, which often are aimed for the highest volume markets. This trend towards a commodity model limits customers' ability to optimize and differentiate, which makes achieving a competitive advantage an increasingly difficult goal.

The presentation describes how the Extensible Processing Platform (EPP) allow designers to target cost sensitive as well as high-performance applications from a single platform using industry-standard tools. The tight integration of the processing system with programmable logic allows designers to build accelerators and peripherals to speed up key functions in hardware, while the ARM architecture and ecosystem maximizes productivity and eases software development.

The Zynq™-7000 family is Xilinx's first Extensible Processing Platform (EPP). This new class of product combines an industry-standard ARM® dual-core Cortex™-A9 MPCore™ processing system with Xilinx 28nm unified programmable logic architecture. The processor-centric architecture offers the flexibility and scalability of an FPGA, combined with ASIC-like performance and power, and the ease of use of an ASSP.

Presenter: Andreas Berg, Silica

Andreas Berg is Technical manager and Field application engineer, with focus on Programmable logic, at Silica. He has a long PLD FAE experience and has also been at  Memec and Lattice. Previous positions include ASIC designer at Mitel Semiconductor, Assistant professor at KTH College of Engineering, and System engineer at Ericsson.

Andreas holds a M Sc EE in Microelectronics from KTH and a Licentiate Degree in Applied Electronics from Lund University.

14:15

A Network On Chip Flexible Interconnect Architecture for FPGA System Designers

FPGA technology has evolved to the state where performance, area and cost are no longer a barrier to providing true system on a chip solutions. However, the complexity of modern systems is a challenge to the FPGA developer; the availability of a wide range of IP shifts the development challenge from functional module development, to the design of a working, high performance, flexible module interconnect in as short a time as possible.

This presentation will describe how a network on chip based interconnect architecture can be used to create higher performance system interconnect in a more scalable fashion compared to a traditional address based system interconnect.

The interconnect architecture is a flexible, modular interconnect architecture, consisting of a collection of interconnect components, network adapters and system generation programs which can convert an abstract system specification and collection of disparate interface IP components into a concrete, realizable system. We will present details of the architecture, its’ performance advantage and how the modular design of the interconnect can be used to easily adapt to different interface standards like Avalon-ST, Avalon-MM, AXI, AHB, OCP, Wishbone, CoreConnect. Opening up the support for an array of Microcontroller architectures on an FPGA.

Presenter: Stefano Zammattio Altera

Stefano Zammattio joined Altera in 2004 and is a Product Manager in the European Marketing group. Mr. Zammattio is responsible for Altera’s embedded products and Industrial applications in the European region, specializing in the Nios II processor and related development tools.  Mr. Zammattio has been involved in the computing and electronics industry since 1987 and holds a BSc in Physics and a MSc in Medical Electronics

15:00

15:30

Hardware IPs as open source - the future of SoC design and FPGA / ASIC development.
Right now there is running a number of interesting FPGA projects based on the open source processor “OpenRISC12000” from OpenCores.org and the associated development platform from ORSoC. Some of the key benefits of using open source Ips for SoC design are:
Minimize “end of life problems”
License “freedom” regarding both licensing costs and lock-in effects.
Full access to source code means faster development, debugging and verification.
Improved copy protection - especially when it comes to using an embedded processor in combination with internal hardware accelerator.

Besides the obvious benefits (some stated above) the major driving force for so many projects in based on open source techology starts right now is that the tool chain and the unique verification environments is state of the art (bleeding edge). In many cases far ahead of the "commercial" options. The OpenRISC1200 processor is now ported to the latest Linux version 2.6.38. Work is continuing on 2.6.39. Even this is ahead of most competitors.

Our presentation will provide an overview of open source within HW.
What type of IPs available?
What is / happens on OpenCores - world's largest site/community for open source development?
What are the major benefits of open source HW (direct and indirect)?
What tools and environments are available?
Who uses this technology today?

To simply summarize one can say that most developers have for a long time understood the great advantages of open source technology. Since about a year back all puzzle pieces are in place, i.e. predesigned platforms, bleeding edge tool chains and unique verification environment. This has opened up for anyone who wants to base their products on OpenCores technology to effectively pursue development projects.

Presenter Johan Rilegård, ORSoC AB

Johan Rilegård, CEO of ORSoC AB.
ORSoC are experts in complex SoC designs and FPGA / ASIC development. We are a world leader in building effective systems based on open source technology from OpenCores. ORSoC owns and operates the site/community OpenCores.org.

16:15

Getting maximum performance out of FPGA designs

The performance and capabilities of modern FPGAs have increased significantly since the first FPGA was introduced 26 years ago.  Despite this, it is common that timing, area, or power constraints are not met. This presentation will mainly focus on various techniques that can be used to improve the timing of high speed FPGA designs.  The techniques that are discussed includes the use of synthesis options and attributes, FPGA friendly design, and manual instantiation of FPGA primitives like lookup tables and flip-flops to handle situations where the synthesis tool cannot be convinced to infer the desired logic. A processor optimized for Xilinx FPGAs will be used as a case study during the tutorial, but the techniques that are discussed are general enough to be applicable to most FPGA designs.

Intended audience: While mainly intended for intermediate level FPGA designers, beginners should be able to grasp the idea behind most of the methods discussed in this tutorial as long as they are familiar with digital design techniques.

Presenter: Andreas Ehliar, Linköping University

Andreas Ehliar is presently an assistant professor in computer engineering at Linköping University. His research interests include FPGA optimized design, coarse grained reconfigurable systems, and application specific processors for multimedia and radio.