09:30

Fixed point SW reference modeling and IEEE fixed point HDL package co-design

60 min tutorial

Developing an algorithm and getting the algorithm onto silicon may in many cases not only be time consuming but also involve several persons with different engineering profiles/disciplines. In any case, implementing an efficient SW model is often crucial to obtain adequate and robust results. This presentation will demonstrate an engineering approach to a design methodology bridging the gap between the algorithm development team and having an implementation running in silicon. The methodology is based on transforming a high level floating point SW model into a full fixed point SW reference model taking advantage of the IEEE fixed point HDL package. By this procedure, the design teams will gain complete control over the algorithm's arithmetic behavior pre-silicon and at the same time reduce the time spent on porting the implementation into silicon significantly. This is a must have for companies searching for a "design pattern" bridging the gap between algorithm development and HW design.

Presenter: Hugo Hedberg, Prevas

Hugo Hedberg received the M.S.E.E. and Ph.D. degrees in Electrical Engineering from Lund University, Lund, Sweden, in 2001 and 2008, respectively. His doctoral thesis addresses hardware accelerators for automated digital surveillance systems. His main research area is hardware implementations of image processing algorithms targeted for real-time embedded systems with a special interest in developing low complexity architectures for morphological operations. He is currently working as a FPGA designer for Prevas AB.