OCT 5,
15:30-17:00
Hi End Board Systems
Chairperson: Johan Nordin, Recab

15:30

 

 

 

 

 

 

 

The way to 40G connectivity

ATCA is rapidly moving into 40G connectivity, which brings number of system architectural issues that need to be addressed. 40Gbit/s is a lot of data to be processed and will require sophisticated packet processing techniques at each point in the ATCA system. ATCA HUBs will be tasked to perform sophisticated Traffic Management and Policing functions, distributing and load balancing packets between multiple payload blades within the chassis. Each payload blade will require to further process the packets and perform second level of Traffic Management and load balancing function so that packets can be efficiently distributed between CPUs on the blade and even between the cores within CPU. This session will explore connectivity within ATCA chassis and how these Traffic Management and Policing functions can be implemented resulting in highest performance data plane processing platform.

Presenter Gene Juknevicius, GE

Gene Juknevicius works as Senior Architect & Technologist at GE Intelligent Platforms and has taken part in PICMG AMC and Micro TCA committees and is an active member of the SCOPE alliance. At GE IP he is in charge of the definition of new products and architectures. Gene holds a M.S. degree in Electrical Engineering from Stanford University.

16:00

 

 

 

 

 

 

 

System design for next generation processing power demands

The invention of the Multi-Core processors was a significant step to increase the processing power in a single silicon. This is influencing the chassis design in several ways. The data transfer rates have to increase significantly. Today typical data transfer rates on the backplane are 1 or 3.25 Gb/s per port. In the near future 10 Gb/s will be needed. The increased processing power generates higher power losses that have to be cooled by the chassis. New cooling concepts have to be introduced. Even the power distribution from power input over the backplane to the boards is getting a challenge as board power consumptions rise up to 400W. The presentation gives an overview about today’s and future data transfer and power demands and what is needed to design a suitable system solution.

Presenter: Udo Weiss, Schroff

Udo Weiss is has been with Schroff since 1994. He is a Field Application Engineer for Systems and has a lot of experience in developing High Power electronic Systems and appropriate cooling solutions.
Udo is holding a Feinwerktechnik (“Mechatronics”) diploma of the Fachhochschule Aalen, Germany.

 

16:30

 

 

 

140Gb throughput in a 1U uTCA system

Utilizing the maximum performance out of a 1U uTCA system. Pointing out design issues in terms of non blocking switching, management, power consumptions, cooling and space for connectivity.

Johan Nordin, CTO RECAB

 

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