13:30

Boosting Platform Performance with Multiple Cores and Hardware Acceleration

As the performance requirements of embedded platforms continue to rise, it is clear that more is required of microprocessors than just increasing clock speeds. Using platforms based on the 2nd generation Intel® Core™ processor family as examples, this presentation will show how multi-core processors and hardware acceleration can help OEM’s deliver solutions that can address the needs of the embedded market segment.

 Presenter; Peter Mayers, Intel

Peter Mayers has been a senior Technical Marketing Engineer with Intel Corporation for the last 11 years. In a career in the electronics industry spanning just over 30 years, he has worked in system design, as a field applications engineer, in PR and in technical support

14:15

How heterogeneous Multi-core processing can change the landscape for x86 based embedded computing

 With the fusion of CPU and programmable GPU performance in a single APU, graphics intensive and data intensive embedded applications receive a massive performance boost. Based on APU technology, an explosion of new opportunities opens new fields of innovative appliances for OEMs in a diverse markets, ranging from automation to medical and military, aerospace and Government (MAG). The migration path to these new appliances based on highly capable, yet low power SFF designs is already paved for a smooth evolution by the new AMD APUs and open standard APIs.

Presenter Jeff Channell, AMD- Firefly

Jeff is a semiconductor industry veteran with 30+ years of experience in selling digital and mixed signal semiconductor solutions. Having spent 26 years in various management positions at Analog Devices, Jeff joined Firefly in 2007 to drive new business development. Firefly Technology are the direct sales representatives for AMD Embedded Solutions in Northern Europe, with Jeff responsible for the interaction with customers in the Nordic regions.

15:00

Break

15:30

SMT pushing high-end Multicore Devices to new heights

With every generation of process technology there is budget to use for higher yet more advances devices. This for long drove higher frequency devices but due to limitations in memory latency has lately been shifted to instead add more cores, interfaces and application specific acceleration. But aggressively increasing the number of cores is not easy without spending an ever increasing die size on interconnection alternatively increased interconnection latency/bandwidth or to give up memory coherency which drastically complicates software development.
The Freescale e6500 core introduces SMT – Simultaneous Multi-Threading, where each hardware thread is given enough resources to execute independently, yet share infrequently used or very expensive core resources. This allows for allows for a very efficient increase in device performance and a low cost at SoC level.
This presentation explains technology challenges and general trends in the market and shows examples based on Freescales next generation high-end multicore flagship device, the 28nm T4240.

Presenter Jonas Svennebring Freescale

Jonas Svennebring is a senior FAE and wireless infrastructure expert within Freescale and has worked as a member of the T4240 system architecture and design team to specify and design the next generation series of high-end QorIQ devices. Jonas has worked for over a decade in the semiconductor industry focusing on networking and telecommunication, device as well as system design and software architecture.

16:00

Evolving the Multi-core DSP Architecture

The following paper looks at the differences between the latest multi-core architecture (Keystone) and previous DSP architectures with respect to how the changes enable users to get the most from the chip. In particular we address the new efficient on-chip engines to aid inter-core communications, mechanisms to access shared internal and external memory, high speed on-chip switch fabric, and external high-speed connectivity options. Not forgetting the usability aspect which needs a comprehensive software development and debug environment including eclipse based IDE, application frameworks and libraries, as well as out-of-the-box real-time operating systems.

With over 25 years experience of developing and promoting DSP technology, Texas Instruments are able to provide a wide range of DSP cores and associated collateral to ensure customers and educators enjoy a successful DSP experience.            

Presenter: Greg Peake, Texas Instruments Europe

Greg Peake is an Applications Engineering manager and a senior member of Texas Instruments’ technical staff. Originally starting as a DSP engineer at Texas Instruments he has had the opportunity to design and program many of TI’s embedded platforms – from MPU to DSP and the integration of both. He is currently leading a team supporting system solutions and embedded processor platforms in Europe for TI’s portfolio of high-performance single-core, and multicore C6000 DSPs.

16:30

Combined Circuit and Electromagnetic Modelling on Multi-core Platforms

Computer simulation techniques are widely used in various fields to design and verify the functionality, performance, quality, or safety of a product. In electrical systems, with increasing operational frequencies, capacitive and inductive couplings between parts in an embedded system might have to be taken into account. Therefore, traditional circuit analysis are not sufficient for such problems. Hence, other simulation approaches such as Partial Element Equivalent Circuit (PEEC), Method of Moments, and Finite Element Methods, and other have been developed to fulfill this need. By using the PEEC method, the simulation of the functionality of an electrical device can be combined with an electromagnetic analysis. Thus, the method has been widely used in combined circuit and electromagnetic modeling on problems in different classes in power electronic industry and antenna design. The main aim of this paper is to demonstrate how multi-core systems can contribute to improve the performance of a PEEC-based electromagnetic simulation tool and to show that the improvements make it possible to solve larger and more complex problems in a reasonable time.

A PEEC-based solver has been developed at Luleå University of Technology. The kernel of the solver has been implemented in C++ and is designed to run on different desktop platforms and operating systems. It is known that in the PEEC formulations there are large, dense, and in many cases nonsymmetric matrices which increase the computational costs. Hence, using an efficient and robust library as well as support for the recently advanced hardware, is vital and will highly affect the performance of the solver.

Presenter: Danesh Daroui, Luleå University of Technology


Danesh Daroui, who will be the presenter of this paper, is a Ph.D. student at EISLAB division, Luleå University of Technology.