09:30

Could Your Software Benefit From Migrating To a Multicore Platform? And If So, Do You Have A Software Development Organization That Could Do It?

Almost every silicon company offers a range of multicore platforms these days, but that doesn't mean that all embedded products are making use of them. Is that because the development organizations have done a thorough analysis of the potential performance benefits of moving their software to a multicore platform, assessed the work required and timescales involved in re-factoring the code to unlock those benefits, and audited their development teams to ensure that they have the required multicore related development skills? Very unlikely!

Although it would be nice to believe that the decision to move or not to move to multicore would be based on sound business principles and extensive analytical data, it's much more likely that developers do not use multicore platforms simply because they don't know how to quantify the benefit in the context of their own code. This presentation will describe the key elements to assessing the why, how and what of a multicore planning process.

Being able to make informed decisions about when and how to migrate today's complex software onto multicore has already become a differentiating capability in today's highly competitive embedded product market. Senior developers and managers need to understand how to upgrade their planning and development processes, as well as their development organizations, such that they can make the best use of the full range of available silicon platforms.

Presenter: David Stewart, CEO, CriticalBlue

David Stewart is the CEO and co-founder of CriticalBlue, a company that develops and distributes software solutions and associated services for migrating existing software applications onto multicore platforms. He is also co-chair of the Multicore Programming Practices (MPP) working group within the Multicore Association. David has over 25 years experience in the embedded software, EDA and semiconductor industries. This includes 10 years at Cadence where he was as a founder and Business Development Director of the System-on-Chip (SoC) Design facility at the Alba Campus in Scotland. This initiative attracted worldwide interest and the Design Centre grew to 200+ people in its first 18 months. Before Cadence he was a chip designer, with spells at LSI Logic, NEC Electronics and National Semiconductor. David has worked for several startups, served on the board of several other small technology companies and been an advisor to a venture capital firm.

10:00

Tackling Software Reliability on Multiprocessor Architectures

To keep pace with customer demands for more functionality and speed, software development teams are moving away from single processor architectures at a rapid rate. However, the overall complexity involved in porting or developing software for multicore and multiprocessor architectures is having a serious impact on software development teams: these software projects are more expensive, have longer schedules, and require significantly more software engineers. One area in particular where growing complexity can have a dramatic impact on cost and schedule overruns is with software testing and code inspection, specifically as it relates to identifying complex concurrency errors and endian incompatibilities. Citing recent research by VDC Research, this session begins with an overview of the challenges being faced by software teams developing code for next-generation devices. It then moves into a technical walkthrough of how state-of-the-art source code analysis technology can be used to find concurrency, endian incompatibility, and other complex software issues.

Presenter Gwyn Fisher, Klocwork

Gwyn Fisher is the chief technology officer at Klocwork and has more than 20 years of global technology experience. He brings a valuable combination of vision, experience, and direct insight into the software developer’s perspective. At Klocwork, Gwyn returns to his original passion, compiler theory, to move static source code analysis to the next level.

10:30

Break

11:00

Multicore and Virtualization: Embedded Synergy

Fostered by the latest embedded multicore processors with virtualization hardware support, a new generation of hypervisor technology is rapidly making its way into a wide range of electronic products. Embedded virtualization has specialized requirements, involving footprint constraints, power efficiency, and reliability. This session will introduce and compare hypervisor implementations across the most popular multicore processors, including ARM® Cortex™, Intel® Atom™, and Freescale™ PowerPC™, and explain how this exciting technology can be practically applied to enable compelling new capabilities across a wide range of industries and embedded applications.

Presenter: Anthony Webb, Green Hills Software

Tony has been an FAE with Green Hills Software since 2008 and specialises in safe and secure embedded applications, particularly the use of INTEGRITY RTOS, hypervisors and associated C and C++ development tools. Tony has worked in various embedded software roles since graduating from Liverpool University in 1997. He has experience developing satellite, airborne and ground based embedded systems across the military and civilian sectors, including navigation, telecommunications and radar systems.

11:30

Harness Multicore Performance with Graphical Programming

The advent of multicore processors offers test, control, and design engineers the opportunity to create higher performance systems capable of solving more complex problems. However, multicore processors present new software challenges you must overcome to fully take advantage of the benefits of multicore hardware resources. During this session, we examine the trend toward multicore processor-based systems and explore how National Instruments LabVIEW software can increase performance on such systems without the need to understand the intricacies of parallel hardware.

Presenter: Björn Beckman, Field Sales Engineer, National Instruments

12:00

15:00

Breaking the Laws of Nature in Multicore Debug

With a full-system simulation, you can break the laws of nature.  In a simulator, you can reverse time, stop everything synchronously, and make race conditions repeat endlessly – just like you can jump a hundred meters high in a video game. Elusive concurrency glitches become repeatable bugs, and heisenbugs are no longer a concern since the simulator can observe without intruding . Bugs can be packaged up and shipped from place to place and developer to developer.  By changing the hardware configuration, latent bugs can be forced to materialize – before software is shipped and a customer finds the issues for you.

Presenter: Jakob Engblom, Wind River

Jakob Engblom is Technical Marketing Manager for the Simics product line at Wind River. He has been working on Simics since 2002, and today works on product planning and how to apply Simics to customer problems.  He holds a PhD in real-time systems from Uppsala University and an MSc in computer science, also from Uppsala University. He has written and presented more than 100 articles and talks over the years, on a variety of embedded systems topics.

15:40

Smart Multicore Embedded Systems - a European research initiative for programming of future embedded platforms

SMECY is a large scale European many-core research initiative driven by a consortium of 30 academic and industrial partners from nine European countries. The mission of the SMECY project is to develop new system design and development technologies enabling the exploitation of future many (100s) core architectures in embedded systems industry. The main contribution is to investigate and develop a complete compilation chain, which controls the design flow from a domain-specific application to a many-core platform.
This talk gives an overall view of the research activities in SMECY and the main goals of the project. The complete set of activities cover both hardware-oriented aspects on processor architecture design, with emphasis on improving hardware interfaces for programmability and novel techniques for supporting fault tolerance, as well as more software-related aspects, including exploration of various forms of programming models and in particular investigation and development of their supporting development tools. The talk will highlight Halmstad University’s contributions and present some of the preliminary results reached in the project so far. www.smecy.eu

Presenter Jerker Bengtsson, Halmstad University

Jerker Bengtsson received his M.Sc. in Computer Systems Engineering from Halmstad University in 2003 and his Ph.D. in Computer Engineering from Chalmers University of Technology in 2009. He is currently appointed as Assistant Professor at Halmstad University and represents Halmstad University in the SMECY Technical Committee. His current research focus is models of computation, parallel programming models and programming tools development for highly parallel processors.

16:20

Dataflow - Parallel Programming with Streams

After decades of unabated performance improvements, sequential computing machines seem to have reachd their terminal velocity. Instead of architecting ever more sophisticated sequential processors, therefore, future computers will become increasingly more parallel. Future applications, in order to be portable, will need to be written in a way that is amenable to efficient implementation on platforms with different architectures and different degrees of parallelism.

Dataflow is a parallel programming model based on the notion of streams and computational kernels processing them. In addition to its simple and intuitive model of concurrency, it is a good match to many of the application areas that show particular demand for processing speed, such as video coding, image and video processing and analysis, digital signal processing, and networking and packet processing.

In this talk I will present some of the features of dataflow as a parallel programming model, and discuss some of the research challenges on the way to making it a practical reality.

Presenter: Jörn Janneck, Dept. of Computer Science Lund University

Jörn W. Janneck is a senior lecturer at the computer science department of Lund University. He received his diploma in computer science from the University of Bremen in 1995, and his PhD in electrical engineering from the ETH Zurich in 2000. Prior to joining Lund University he worked at the United Technologies Research Center in Berkeley, CA and at the Xilinx Research Labs in San Jose, CA. He was a visiting postdoctoral scholar at the University of California at Berkeley and a researcher at the Fraunhofer Institute for Material Flow and Logistics in Dortmund.

His research interests include various aspects of the description and construction of concurrent and parallel computing systems. More recently he has been focused on the use of dataflow as a programming paradigm for parallel platforms in stream processing application domains, and specifically programmable logic devices and multicore machines, working on the design of programming languages and corresponding tools for translating, profiling, and analyzing dataflow programs. His work has significantly shaped the recent MPEG/ISO standards activities to restructure the normative description of video codecs as dataflow programs.